The present invention relates, in general, to the field of nonvolatile memory devices. More particularly, the present invention relates to a nonvolatile memory device utilizing a single transistor as the only element in the memory cell and a method for the formation of such an element incorporating a ferroelectric material as the gate dielectric thin film formed at a relatively high temperature.
Nonvolatile ferroelectric random access memory (xe2x80x9cFeRAMxe2x80x9d) devices represent an emerging, multibillion-dollar market. The most advanced FeRAMs utilize a 1-transistor/1 capacitor (xe2x80x9c1T1Cxe2x80x9d) cell technology and a destructive read out (xe2x80x9cDROxe2x80x9d) scheme. These devices compete with electrically erasable programmable read only memory (xe2x80x9cEEPROMsxe2x80x9d), battery backed static random access memory (xe2x80x9cRAMxe2x80x9d; xe2x80x9cBBSRAMsxe2x80x9d), and Flash nonvolatile memory devices.
FeRAM is a type of semiconductor memory, constructed similarly to a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) device, but which stores bits of data without the need for a continuous power requirement (nonvolatile characteristic). FeRAMs have gained recent interest because of the possibility that they could become the ideal memory of the future, also replacing standard mass-produced DRAM. Although the basic fundamentals of ferroelectricity were discovered in the 1920""s, developments within the last fifteen years regarding the use of thin ferroelectric films may now make it practical to develop a dense memory with ideal nonvolatile memory performance characteristics. Ferroelectric materials exhibit ferroelectric behavior below a critical temperature, known as the Curie temperature. The Curie temperatures of many ferroelectric materials are above 200xc2x0 C. allowing them to be used as storage elements for nonvolatile semiconductor memories.
Conventional FeRAMs operate using an array of memory cells, which contain capacitors, built of a special dielectric material (a ferroelectric) sandwiched between two conducting material (electrode) layers. The special ferroelectric material is comprised of a lattice of ions, in which one of the ions in each unit cell has two stable states on either side of the center of the unit cell along an elongated axis as shown in FIGS. 1A and 1B. When a voltage is applied across the top and bottom electrodes of a ferroelectric capacitor, the movement of these charged center ions creates a charge displacement within the dielectric. This charge displacement can be sensed as a current flowing between the electrodes of the ferroelectric capacitor. The charge displacement within a ferroelectric capacitor is often displayed as a hysteresis curve, where the polarization (or polarization charge) of the ferroelectric layer is plotted against the applied electric field (or applied voltage), as shown in FIG. 1C.
FIG. 1D shows a schematic of a conventional 1T1C memory cell. When a positive voltage is applied across a negatively polarized ferroelectric capacitor, the center ions of the unit cells switch to positively polarized states. This ion movement can be sensed as a current flow between the electrodes of the ferroelectric capacitor. When this voltage is removed, the polarization settles to the state labeled xe2x80x9c+Q0xe2x80x9d (See FIG. 1C). If a negative voltage is then applied across the ferroelectric capacitor, the center ions of the unit cells switch to negatively polarized states. When this voltage is removed, the polarization settles to the state labeled xe2x80x9cxe2x88x92Q0xe2x80x9d. FeRAMs offer an advantage over DRAMs because ferroelectric polarization can be retained in either state, +Q0 or xe2x88x92Q0, for a very long time (retention) without continuously applied power (non-volatility). Unlike other nonvolatile memory elements, ferroelectric capacitors can be switched from state to state many times (currently  greater than 1010 cycles) without wear-out (fatigue). Also, because the ferroelectric capacitors operate at a relatively low voltage, there is no need for high voltages provided by charge pumps to program (or xe2x80x9cwritexe2x80x9d) the memory as required for certain nonvolatile memories (e.g., EEPROM and Flash). These low programming voltages ultimately allow ferroelectric memory cells to scale to smaller dimensions than Flash memory and improve radiation hardness.
Conventional techniques for processing FeRAMs require the fabrication of ferroelectric capacitors after all of the underlying complementary metal oxide semiconductor (xe2x80x9cCMOSxe2x80x9d) circuitry has been fabricated just prior to metalization. A typical cross section of a 1T1C cell would exhibit a ferroelectric capacitor placed on the field oxide which is connected to the associated pass transistor with a local interconnect. This presents a significant processing difficulty, because the proper ferroelectric phase has to be formed after deposition by a high temperature anneal operation, preferably in an oxygen atmosphere. When the underlying CMOS circuitry is heated to high temperatures, hydrogen is released, which degrades the ferroelectric film. Depositing the metalization interconnect layers can also produce hydrogen. Thus, a hydrogen barrier must be added to protect the ferroelectric capacitors. Also, some ferroelectric materials are very sensitive to moisture, which contamination can be formed when hydrogen is released. Finally, when relatively dense memory arrays are fabricated, planarization techniques are commonly used. Most processes require interconnect metalization to be added before the ferroelectric materials are deposited and activated. This interconnect metalization will generally not withstand the high temperatures of ferroelectric film activation. All of these problems have slowed the development of dense FeRAMs and have clouded the future for an ideal memory.
A particularly significant disadvantage of prior art 1T1C cell memories is that, under the best of circumstances, they cannot be scaled aggressively enough to compete with Flash memory since they require 2 elements per cell compared to a single element in Flash devices. With comparable design rules, a conventional FeRAM device will exhibit a cell size at least twice the cell size of Flash memory.
Disclosed herein is a memory cell, device and method for producing the same which advantageously includes a memory cell comprising a single transistor. This transistor is formed, for example, utilizing a rare earth manganite as the thin film ferroelectric material that forms part of the gate dielectric of the ferroelectric transistor. This ferroelectric gate material may be deposited directly on silicon instead of a metallic or conductive oxide bottom electrode as in prior art ferroelectric devices. In order to form a ferroelectric transistor, the ferroelectric material has to be inserted relatively early in the CMOS process. It has, therefore, to be able to withstand higher temperatures, most likely up to and on the order of 950xc2x0 C., (e.g. the activation temperature for the implanted source and drain junctions).
The requirements for the ferroelectric gate material in accordance with the technique of the present invention are quite different from the ones encountered in a conventional 1T1C cell. In addition to the high temperature requirements, it should also have a relatively low dielectric constant, preferably on the order of less than 20. The reason for this is that any ferroelectric material deposited on silicon forms an interfacial layer with a rather low dielectric constant, most likely around 3.9, the value for SiO2. A voltage applied to the gate of the transistor is, therefore, divided between the ferroelectric material and the interfacial layer. If the capacitance of the interfacial layer is much smaller than the capacitance of the ferroelectric layer, most of the voltage will drop over the interfacial layer and is not available for switching the ferroelectric material. It is, therefore, not possible to operate the device at low voltages. The ferroelectric material and technique of the present invention exhibits a low relative dielectric permittivity of around 10 and forms an interfacial layer with a relative dielectric permittivity larger than that of SiO2, which makes it particularly suitable for a 1T cell.
The ferroelectric material of the present invention is also substantially different from known ferroelectric materials such as lead zirconate titanate (xe2x80x9cPZTxe2x80x9d) and strontium bismuth tantalate (xe2x80x9cSBTxe2x80x9d), which are the preferred ferroelectric materials in current use. A device in accordance with a preferred embodiment of the present invention may include a substrate such as silicon, a thin film of a rare earth manganite (or xe2x80x9cmanganatexe2x80x9d; the terms may be used in an equivalent sense herein since a broad range of compositions is contemplated [i.e. x,y,z from 0.1 to 10] with the term xe2x80x9cmanganatexe2x80x9d usually being associated with a +2 oxidation state and the term xe2x80x9cmanganitexe2x80x9d being associated with a +3 oxidation state) as the ferroelectric material deposited directly onto this substrate and an electrode formed on top of the ferroelectric material. Source and drain regions may be formed either before or after the ferroelectric layer deposition. The device is provided with contacts to the source and drain regions and to the gate electrode. Standard metalization (e.g. aluminum, or other conductive materials) is used to connect these contacts to other elements in an integrated circuit device, such as a CMOS circuit, and to external circuit elements.
The ferroelectric material utilized in the implementation of the present invention, as previously mentioned, may be deposited directly on silicon and is composed of any rare-earth manganite, or similar materials such as Yttrium manganite or Scandium manganite, with the formula AxMnyOz (where A=Y, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu or Sc) and x,y,z are substantially between 0.1 and 10.
The rare earth manganites used in a representative implementation of the present invention have been demonstrated to possess the desired properties for successful operation of a 1T memory cell. Further, they appear to have typical dielectric permittivities of less than 20, they generally form a stable interfacial layer with a relatively high dielectric constant of xcx9c30, they exhibit high transition temperatures (Curie temperature) of typically  greater than 600xc2x0 C. and they have inherently low mobile charges (e.g. oxygen vacancies). In order for 1T devices to exhibit good retention, mobile ionic charges in the ferroelectric film have to be minimized. Rare earth manganates have low oxygen vacancy concentration, the most significant of the ionic mobile charges. Still further, the ferroelectric polarization is in the ideal range of substantially 0.1 to 2 xcexcC/cm2.
Rare earth manganites are high temperature materials which means that they are ideal for forming ferroelectric transistors which have to withstand a considerable thermal budget. Most rare earth manganites (e.g. YMnO3 and CeMnO3) require a high temperature treatment (anneal) of typically at least 850xc2x0 C. in an O2 atmosphere for approximately an hour in order to form the proper ferroelectric phase. The processing window is approximately 100 to 200xc2x0 C., which means that they are able to withstand heat treatments of 950 to 1050xc2x0 C., well above the thermal budget of a modern CMOS process.
The ferroelectric materials utilized in the implementation of the present invention may be deposited, preferably, by metallorganic chemical vapor deposition (xe2x80x9cMOCVDxe2x80x9d) techniques, although other methods such as plasma enhanced chemical vapor deposition (xe2x80x9cPECVDxe2x80x9d), metal-organic decomposition (xe2x80x9cMODxe2x80x9d) or other techniques could be used. In a representative embodiment of the present invention, the MOCVD process may be preferred as it tends to minimize ionic contamination (e.g. Na+) which is detrimental to data retention in a final 1T cell device. The MOCVD process may preferably employ a liquid source delivery and flash evaporation method, since the precursors preferably used typically have low vapor pressure, making other methods such as vapor delivery with bubblers more difficult. Examples of precursors which might be used for CeMnO3, used in a particular embodiment of the present invention, are Cerium (IV) tris-tetramethylheptanedionate (thd) for Cerium (Ce) and Manganese (III) tris-tetramethylheptanedionate for Manganese (Mn). These materials are solid powders and can be brought into solution with tetrahydrofuron (xe2x80x9cTHFxe2x80x9d) as the solvent with tetraglyme added to prevent any early evaporation problems.
The exemplary MOCVD process disclosed herein produces rare earth manganite thin films with low mobile ion contamination, excellent uniformity, good step coverage and excellent compositional control. Importantly, it produces a well controlled interfacial layer of SixOyAz that is enhanced by the subsequent anneal steps in O2.